The present disclosure relates to semiconductor integrated circuit devices applicable to flip-chip mounting, and a method for designing the same.
As technologies for manufacturing semiconductor devices continue to progress in densification and miniaturization, the number of transistors constituting a large scale integrated circuit (LSI) continues to increase. As the number of components constituting the LSI increases, increase in area of a semiconductor chip is a growing concern. Thus, reducing the area of the chip is one of the most important issues in view of reduction in manufacturing cost. In general, a wire bonding method is employed to connect the LSI and a package for mounting the LSI. When this mounting method is employed, input/output (IO) cells of the LSI are arranged on a peripheral portion of the semiconductor chip.
The above-described structure is disadvantageous because the chip area increases depending on the number of the input/output cells. Further, when the wire bonding method is employed, wires have to be press-bonded to the input/output cells, and the input/output cells need a predetermined size or larger to maintain their strength so that the input/output cells do not break when the wires are press-bonded thereto. Since a certain area is required in press-bonding the wires, the input/output cells cannot be physically reduced in size. Accordingly, in a miniaturization process, the chip area is limited by the input/output cells when the number of the input/output cells in the chip increases. Even when a technique of synthesizing placement of internal logics is used to reduce the area, the chip area cannot be reduced as a whole.
A solution to the above-described disadvantage is a flip-chip structure. FIG. 17 shows a structure of a semiconductor chip constituting a conventional flip-chip semiconductor integrated circuit device in a plan view, and FIG. 18 shows a cross-sectional view of the structure of the flip-chip semiconductor integrated circuit device. As shown in FIG. 17, a plurality of pads 12 are arranged on an entire region of an upper surface of a chip (LSI) 21. The pads 12 are electrically connected to input/output cells 11 arranged on a peripheral portion of the chip 21 through interconnects 13 called redistribution interconnects, respectively. FIG. 18 shows a cross-sectional view of the chip 21 of FIG. 17 connected to a package 22.
As shown in FIG. 18, the chip 21 is fixed face down to a surface of the package 22, and is electrically connected to the package 22 through the pads 12. The chip 21 on an upper surface of the package 22 is coated with a sealing resin 23. A plurality of external electrodes 24 are provided on a rear surface of the package 22. When this flip-chip structure is employed, wiring between the pads 12 and the input/output cells 11 is no longer necessary, and the input/output cells 11 can be reduced in size as compared with those of the conventional structure. Further, there is no need to arrange the multiple input/output cells 11 only on the peripheral portion of the chip 21, i.e., on the peripheral portion of the LSI. This can resolve the disadvantage involved in the wire bonding method, i.e., the area of the LSI is determined by the input/output cells 11.
In the following description, the pads 12 arranged on the entire surface of the chip 21 in a flip-chip manner will be referred to as area pads.
In the flip-chip structure, the interconnects 13 connecting the area pads 12 arranged on the surface of the chip 21 and the input/output cells (10 cells) 11 arranged on the peripheral portion of the chip 21 have to be efficiently designed. Specifically, when the number of the area pads 12 is drastically increased by forming the area pads on the entire surface of the chip, the number of the interconnects between the area pads 12 and the input/output cells 11 increases, and length of the interconnects increases.
Unless this problem is solved, the chip area increases, and timing performance of the interconnects 13 connected to the input/output cells 11 cannot satisfy predetermined requirements. This may reduce performance of the LSI.
As a solution to this disadvantage, Japanese Patent Publications Nos. 2003-007750 and 2007-173388 teach a technique of placing the area pads on the peripheral portion at an increased pitch, thereby allowing efficient routing of the interconnects between the area pads and the input/output cells.